-- ELEC4605 Computer Engineering
-- Reg8OEDIR.Vhd
-- Peter Stepien
-- 2005

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reg8oedir is
  port(ck, oe, dir : in std_logic;
       a           : inout std_logic_vector(7 downto 0);
       b           : inout std_logic_vector(7 downto 0));
end;

architecture behaviour of reg8oedir is
  signal lq : std_logic_vector(7 downto 0);
begin

  Latch: process (ck)
  begin
    if (ck='1' and ck'event) then
       if dir='0' then
         lq <= a;
       elsif dir='1' then
         lq <= b;
       end if;
    end if;
  end process;

  -- Output_Enable
  b <= lq when ((oe='1') and (dir='0')) else "ZZZZZZZZ";
  a <= lq when ((oe='1') and (dir='1')) else "ZZZZZZZZ";

end;