2.5.2. Layout Vs Schematic (LVS)
Now that we have the custom layout design of the inverter, we can check that all the wiring of our pins and transistors follow that of the schematic wiring. During typical designs of a custom layout, it can become easy to forget a wiring, or to accidentally cross wires, especially for larger designs than the inverter presented here within this tutorial. To do this we will go through the steps required in performing a Layout versus Schematic (LVS) test.
To perform this test we have to first make an extracted view of the layout, which just creates all the connections within the circuit and provides any parasitic capacitors that are generated from the design of our layout. Parasitic capacitances are due to a capacitance affect occurring between layers, as well as between two instances within the same layer. Recall - a capacitor is just two conductors separated by an insulator. A good layout tries to minimise the values of this parasitic capacitor through good design, as it can affect the speed of your circuit.
(i) Firstly, close the “layout_good” widow and reopen the “layout_bad” view to illustrate how this test can pick up on incorrect wirings (we will come back to the good layout at the end, once the steps for a LVS are presented for a badly designed layout). From this layout view we create an extracted view, by clicking on “verify” and selecting “Extract” (refer to screenshot 27).
Screenshot 27: Creating an extracted view
Within the new “Extractor” window (refer to screenshot 28), we need to make sure that the parasitic capacitances are extracted along with our circuit. This is easily done through adding the “Extract_parasitic_capacitors” to the “Switch Names” parameter. This is done by selecting “Set Switches” and highlighting the “Extract_parasitic_capacitors” parameter. Once this parameter is highlighted, click “ok” to create the extracted view.
Once an extracted view is created we just check that no errors occur during the process, by checking the Command Interface Window”, which should give you no errors for this tutorial (refer to screenshot 29).
Screenshot 29: Error Log from extraction
(ii) Next step, close the layout view and open the “extracted” view to perform the LVS test (refer to screenshot 30). Once again you will notice that there are red boxes representing our components (transistor and capacitors here) and can be changed to show us the schematic view by pressing Shift+k.
Screenshot 30: Extracted View
(iii) To start the LVS test, click on “verify” and select “LVS” to start up the test window (refer to screenshot 31).
Screenshot 31: Starting LVS
A new window will open from which we can run the LVS test from (refer to screenshot 32). As you may notice the parameters for which to run the test may not be given. Simply click browse and select the inverter schematic and extracted, and this will populate with the correct values.
Screenshot 32: Setting parameters in LVS
(iv) Running LVS test, you click on the “run” button the LVS will start and a window will pop up when it has finished (refer to screenshot 33).
Screenshot 33: LVS simulation completion
(v) First Checking Output - there are two ways to check the results of the test. Firstly, by observing the output from the test from clicking on the “Output” button and reading over the results, checking if the schematic and extracted views match (refer to screenshot 34). You will notice for the extracted view of layout_bad, your nets won''t match, meaning there are a different number of wires (refer to screenshot 35).
Screenshot 34: Results opening LVS Output log
Screenshot 35: Results LVS Output log
(v) Second Checking Output – the previous output results do not give you as much specifics as you may need in solving the problem here. So, alternatively once we know there are errors it can be easier for the program to just show us where and what these errors are on our extracted view (or schematic) by clicking “Error Display” button (refer to screenshot 36).
Screenshot 36: Results opening Error display
A new error display window appears from which we can cycle through the errors, highlighting errors spots in purple on the extracted that don''t match the schematic, while a brief explanation on the error is given (refer to screenshot 37). You may notice that there are 4 errors listed here, however there is only really 1 error in that two pieces of metal are not connected that should be. This results from the error in question causing several mismatches, i.e. a missing connection to a transistors, two nets where there is suppose to be one etc. This can lead to a time consuming approach to track down real causes of errors in larger circuits. You can cycle through the errors by clicking on “Next” and “Prev”.
Screenshot 37: Error Display window
(vi) Now, if you perform the same test except extracting the “layout_good” view, you can see that the connection is fixed and there are no differences between the schematic and extracted in the “Output” (refer to screenshot 38).
Screenshot 38: Results LVS correct Output log