The University of Sydney - Computing & Audio Research

3.4. CMOS Register – Simulation

To perform this test lets first close any view open from the previous section and open up the “DFF_wCb_test” circuit “schematic” from the library. You will now notice that there is now a block representing the DFF with a series of inputs and two outputs Q and its inverse Qb. This DFF presented here also has a clear signal, which will hold the output at 0V regardless of the input clk and data signals, whenever this input signal, Cb, goes to 0V (refer to screenshot 48). We want to open up the Analog Design Environment through clicking “Tools” then selection “Analog Environment”.

Screenshot 48: DFF simulation start

From the Virtuoso Analog Design Environment click on “Session” and select “Load State”. Select “test1” and click “ok”. Start the simulation by clicking on “Netlist an Run” (refer to screenshot 49).

 

Screenshot 49: DFF simulation load

Once the simulation is finished from running the output waveform will be given as shown below (refer screenshot 50). You will notice that the output will follow the input once the rising edge of the clk signal occurs.

Screenshot 50: DFF simulation results

Challenges to Students!

For the adventurous type… let’s try something… 

Background - From the previously DFF circuit (refer to section 4.3) we implemented a 1-bit Register. We can expand that, to now be a series of 8-bit Registers – they include Parallel In Parallel Out (PIPO), Parallel In Serial Out (PISO), Serial In Parallel Out (SIPO), and Serial In Serial Out (SISO). These different registers are used for transferring data from/to serial to/from parallel data lines and for buffering serial/parallel data.

Task - Open up one or more tests, relating to 8 bit Registers stating above. Try varying the parameters for the test and observe the operation of the behaviour of the Registers.