JunKyu Lee 

Research Associate

Computer Engineering Lab
School of Electrical and Information Engineering
Room 856, Building J03, Maze Cresent
University of Sydney, NSW, 2006
Australia

Phone: +(612) 9351 4491

Email: jun.kyu.lee@sydney.edu.au 

Research Interests

My broad research interests include :

  • Kernel-based Machine Learning
  • Computer Architecture
  • Reconfigurable Computing
  • Numerical Linear Algebra / Numerical Analysis 

My current particular research includes :

  • Low Latency FPGA-based Machine Learning on a FPGA NIC 
  • Lower Precision (or Mixed Precision) Machine Learning Algorithm

Publications

N. J. Fraser, D. J. M. Moss, J. Lee, S. Tridgell, C. T. Jin and P. H.W. Leong?,"A Fully Pipelined Kernel Normalised Least Mean Squares Processor For Accelerated Parameter Optimisation", International Conference on Field Programmable Logic and Applications (FPL), September 2015 (Paper)

J. Lee, G. D. Peterson, “The Role of Precision for Iterative Refinement,” in Symposium on Application Accelerators in High Performance Computing, 2012. (Poster) 

G. Liang, J. Lee, G. D. Peterson, “ALU Architecture with Dynamic Precision Support,” in Symposium on Application Accelerators in High Performance Computing, 2012. (Paper)

J. Lee, G. D. Peterson, “Iterative Refinement on FPGAs”, in Symposium on Application Accelerators in High Performance Computing, 2011. (Paper)

J. Lee, J. Sun, G. D. Peterson, R. J. Harrison, R. J. Hinde, "Power-Aware Performance of Mixed Precision Linear Solvers for FPGAs and GPGPUs," in Symposium on Application Accelerators in High Performance Computing, 2010. (Paper) 

J. Lee, J. Sun, G. D. Peterson, R. J. Harrison, R. J. Hinde, "Accelerator Performance Comparison for Mixed Precision Linear Solvers," in IEEE Symposium on FCCM, 2010. (Poster)

J. Lee, G. D. Peterson, R. J. Hinde, R. J. Harrison, "Mixed Precision Dense Linear System Solvers for High Performance Reconfigurable Computing," in Symposium on Application Accelerators in High Performance Computing, 2009. (Paper)

J. Lee, G. D. Peterson, R. J. Harrison, R. J. Hinde, "Hardware Accelerated Scalable Parallel Random Number Generators for Monte Carlo methods," in IEEE Midwest Symposium on Circuits and Systems, 2008. (Paper)

J. Lee, G. D. Peterson, R. J. Harrison, “Hardware Accelerated Scalable Parallel Random Number Generators”, in Reconfigurable Systems Summer Institute, 2007. (Poster)