Michael Frechtling


PhD Student

Computer Engineering Lab

School of Electrical and Information Engineering

Room 840, Building J03, Maze Cresent

University of Sydney

Australia 2006

 

Tel: +61 2 9351 7207 | Mob: +61 459 362 692

Email: michael.frechtling@sydney.edu.au

Biography

Michael Frechtling received his BE (Hons) in Computer Systems Engineering from the University of Auckland in 2008. During this time he focused on Embedded system design using hardware description languages such as VHDL, and FPGAs. For his final year research project he collaborated on the modelling and development of a hardware accelerated H.264 video decoder, developing a SystemC model for testing VHDL modules used in the system.

From 2009-2010 he was employed by Horizon Survey Company, an offshore surveying contractor in the United Arab Emirates. His roles with the company included Survey Engineer, ROV Pilot and ROV Video Processor.

Currently, he is a PhD student at the University of Sydney, working on optimization of error analysis in computer arithmetic through H/W acceleration.

Publications

Book Chapters:

  • Michael Frechtling and Philip H.W. Leong. An FPGA-based floating point unit for rounding error analysis. In Wayne Luk and George Constantinides, editors, Transforming Reconfigurable Systems. Imperial College Press, 2013. to appear.

Research Interests

Michael's research is focused on the optimization of methods for run-time error detection in computer arithmetic, and is currently working to implement a Monte-Carlo Arithmetic (MCA) library capable of being applied to C-based projects without significant changes to existing source code. 

General Research Interests:

  • Embedded System Design
  • HW/SW co-design
  • Field Programmable Logic and Hardware Description Languages
  • Computer Arithmetic