FPT 2009 Workshop on FPGA Architectures and Applications

FPT 2009 Workshop on FPGA Architectures and Applications

Overview

This public workshop is in conjunction with the International Conference on Field Programmable Technology 2009. Leading researchers have been invited to give their views on fruitful and unfruitful directions for research in FPGA architectures and applications. Registration is not necessary.

Date: 2-6pm Tuesday 8th December 2009
Venue: Electrical Engineering Lecture Theatre 2 (Rm 450), University of Sydney (directions)
Cost: Free
Speakers and Schedule:
Organisers: Philip Leong (University of Sydney) and Chris Nicol (NICTA). For more information contact Philip Leong

Abstracts and Biographies

Andre DeHon - Architecture of FPGAs as Future Computing Platforms

To date FPGAs have found a healthy niche as an ASIC alternative for the underprivileged. They have thrived in this niche using technology hand-me-downs driven by more popular and affluent products like microprocessors. While they offer a unique combination of programmability, performance, and energy efficiency, it requires herculean effort to extract the performance and energy benefits. Simplified parallel processing on GP-GPUs and multicore processors (e.g. CUDA, Open-CL), now provides an easier and more accessible path to some of the potential FPGA performance benefits. Some experts suggest this trend squeezes FPGAs out of their traditional niche.

We believe technology trends actually favor FPGA-like architectures. However, complexity trends, difficult programmability, and the need to take a backseat to microprocessor-driven fabrication processes, can negate the FPGA's inherent advantages. What would it take for FPGAs to instead take the lead? Where can FPGAs go that ASICs, GP-GPUs, and multicore processors may not be able to go? What changes if FPGAs can drive technology? What must FPGAs do differently to become contenders? How do we get beyond FPGAs as Verilog-Engines and power-hungry ASICs and make them desirable Compute Engines?

We will provide background and frame these questions. We have some of our own ideas about the directions. Nonetheless, we're most interested in leveraging the workshop format to foster active community exploration of these issues. Bring your own questions, thoughts, and opinions, and let's see what we can discover.

This session may not tell you:

But, it will discuss the technology and computational landscape in which these questions should be evaluated if we want FPGA-like designs to be the most effective computing platforms of the future.

Andre DeHon received S.B., S.M., and Ph.D. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 1990, 1993, and 1996 respectively. From 1996 to 1999, Andre co-ran the BRASS group in the Computer Science Department at the University of California at Berkeley. From 1999 to 2006, he was an Assistant Professor of Computer Science at the California Institute of Technology. Since 2006, he has been an Associate Professor of Electrical and Systems Engineering at the University of Pennsylvania. He is broadly interested in how we physically implement computations from substrates, including VLSI and molecular electronics, up through architecture, CAD, and programming models. He places special emphasis on spatial programmable architectures (e.g. FPGAs) and interconnect design and optimization.

Guy Lemieux - "Future Trends in FPGA Interconnect"

In this talk, we present the basics of mesh interconnect design including switch blocks, connection blocks, input interconnect blocks and single-driver wiring. Then we look at application areas that can serve as market drivers for future FPGAs. This is followed by the presentation of various interconnect metrics used to judge the 'goodness' of an interconnect architecture and how to push the envelope to maximize these metrics individually. Finally, we present a variety of open research problems in FPGA interconnect design.

Guy Lemieux received the B.A.Sc. degree from the division of engineering science at the University of Toronto, and the M.A.Sc. and Ph.D. degrees in electrical and computer engineering at the University of Toronto. In 2003, he joined the Department of Electrical and Computer Engineering at The University of British Columbia, where he is now an Associate Professor. He is co-author of the book Design of Interconnection Networks for Programmable Logic (Kluwer, 2004). His research interests include FPGA architecture, interconnect design, computer-aided design algorithms, VLSI and SoC circuit design, and parallel computing. He received a Best Paper Award at FPT 2004.

Mark Shand - "Reconfigurable Computing Research at DEC: a personal retrospective"

FPGAs are 25 years old next year; FPGA based reconfigurable computing is almost as old. Since the late 1980s a growing number of researchers around the world have been exploiting FPGA technology to to explore novel computer architectures and computing paradigms. Digital Equipment Corporation's Paris Research Lab was among the pioneers.

This talk gives an overview of the PAM project and various follow-on developments including PCI Pamette and the Sepia scalable image rendering system. We discuss the various technologies that were developed in support of these reconfigurable systems, the context in which they were developed and the lessons learned, both academic and industrial.

Mark Shand received B.Sc (Hons), and Ph.D. degrees in Computer Science from the University of Sydney in 1982, 1988 respectively. From 1987 to 1988, was seconded from the CSIRO to the VaST lab at the University of NSW. From 1988 to 2006, he held research positions at Digital Equipment Corporation, Compaq Computer Corporation and Hewlett Packard Corporation, in Paris, France and Palo Alto, California. In 2006, he joined Let It Wave, a fabless semiconductor startup specializing in advanced video processing, as Vice President of Engineering. In 2008 Let It Wave was acquired by Zoran Corporation where he is now employed as Senior Principal Architect. His interests span efficient computation in all its guises and the transformation of abstract algorithms to practical realizations.